Engineering substrate through wafer bonding

New, cutting-edge engineering materials can be created through wafer bonding, with properties superior to single materials. However, these bonded materials often de-bond in high-temperature annealings due to CTE(constant of thermal expansion) mismatches. Through decades of research, we have developed a proprietary low-temperature annealing process. The bonding strength in this low-temperature process is equivalent to that of one annealed at high-temperatures. With wafer thinning and exfoliation technology, the following engineering substrates have been developed:

Bonded Wafers Characteristics Applications
Silicon on glass
  • 1. Transparent substrate
  • 2. High dielectric properties of substrate
  • 3. Single crystal of silicon layer
Display, RF device
Silicon on sapphire
  • 1. Excellent electrical insulator, reduce radiation induced current
  • 2. resistant to harsh environment
RF device , MEMS sensors
Silicon on quartz
  • 1. Thermal stability of handle wafer
  • 2. transparent substrate
RF Device
III-V compound on silicon III-V compound device integrated with CMOS device Silicon photonics
GaN on silicon
  • 1. Low cost
  • 2. Less stress of GaN layer , better properties
LED
GaN on diamond/silicon Excellent thermal dissipation of diamond Power device
PZT on silicon Thin layer PZT integrated to MEMS MEMS ultrasonic device, MEMS sensor, energy harvesting device