Reading a wafer specification

The notation used in our inventory listings, the vocabulary of SOI and bonding, and a couple of tools we reach for every day.

Listing notation

Notation	Meaning
P/B	P-type, boron doped
N/P	N-type, phosphorus doped
N/Sb	N-type, antimony doped (often heavily doped, low resistivity)
N/As	N-type, arsenic doped (often heavily doped, low resistivity)
<100>, <110>, <111>	Crystal orientation of the wafer surface. Also written (1-0-0) in our silicon listings.
(D) / (H)	In SOI listings, marks a value that applies to the device (D) or handle (H) wafer only.
BPR, P.R	Device thickness prepared per request on order.
±5% (BOX)	Buried oxide thickness uniformity.
SSP / DSP	Single side polished / double side polished.
P / E	Polished / etched backside finish.
Semi flat, notch, JEIDA	Orientation marker on the wafer edge: SEMI-standard flat, a notch (200 mm and up), or JEIDA (Japanese standard) flat.
Prime, test, excess, mechanical	Grade. Prime meets full surface spec; test and mechanical grades suit process monitors and handling; excess is surplus production.
EPI	Epitaxial layer grown on the wafer surface.
LTO	Low-temperature oxide, typically used as a backside seal.

Device layer 100 nm – 200 µm

Buried oxide (BOX) up to 15 µm

Handle wafer from 100 µm

Use these definitions to compare SOI wafer lots or prepare a custom SOI specification.

SOI (silicon on insulator): A thin single-crystal silicon device layer separated from a thick silicon handle wafer by an insulating buried oxide. Used to isolate devices and as a precise etch stop in MEMS.
Device layer: The top silicon layer where structures or circuits are built. Its thickness and uniformity set mechanical and electrical behavior.
Buried oxide (BOX): Silicon dioxide between device and handle. Thermal oxide is grown; CVD oxide is deposited.
Handle wafer: The thick substrate that gives an SOI wafer its mechanical strength.
CZ (Czochralski): Crystal growth by pulling a seed from molten silicon. The workhorse for most silicon wafers.
FZ (float zone): Crystal growth by passing a molten zone along a rod, giving very high purity and high resistivity — used in RF, detectors and power devices.
Smart Cut: A layer transfer process using hydrogen implantation and splitting. Thick or heavily doped layers usually need extra epitaxy.
Anodic bonding: Bonding silicon to sodium-containing glass with heat and an electric field; ion migration creates a strong, permanent bond.
Fusion bonding: Direct bonding of clean, flat surfaces followed by annealing — the basis of bonded SOI.
TTV, bow, warp: Flatness measures: total thickness variation across the wafer, and how far the wafer deviates from a plane.
CMP: Chemical mechanical polishing, used to planarize and thin wafers to a mirror finish.

2″50.8 mm

3″76.2 mm

4″100 mm

5″125 mm

6″150 mm

8″200 mm

12″300 mm

Micrometers

µm

Nanometers

Ångströms

Mils

mil