SOI wafers explained

One wafer, three different jobs

Silicon on insulator (SOI) is a layered substrate: a silicon device layer sits above an insulating layer, usually silicon dioxide, supported by a silicon handle wafer. In a conventional bulk silicon wafer, there is no buried insulating layer separating the top silicon from the substrate below.

The device layer is the silicon in which structures or devices are formed. The buried oxide (BOX) separates it electrically from the handle, which supports the stack. These layers must be specified individually: “wafer thickness” alone does not describe an SOI wafer.

What the buried oxide makes possible

In MEMS fabrication, the BOX can serve as an etch stop beneath a patterned silicon layer. It can also be removed selectively as a sacrificial layer to release structures. Device-layer thickness then becomes a key dimension of the finished structure. The process still needs an etch and release strategy appropriate to the design.

SOI is also used in RF and power-device platforms. Choosing an SOI substrate for one application does not establish suitability for another: layer thicknesses, electrical properties and the downstream process matter. Okmetic’s SOI overview describes these layer roles and application areas.

Which SOI wafer fits your application?

MEMS, RF, photonics and logic can use SOI for different reasons. Start with the process requirements below; an SOI label alone does not make two substrates interchangeable.

For the underlying technologies, see UCLouvain’s RF substrate research, Soitec’s photonics platform and Soitec’s FD-SOI platform. These describe general application requirements, not a claim that MEMS Engineering supplies every platform listed.

MEMS Engineering SOI wafers in published research

Two peer-reviewed studies identify MEMS Engineering as their SOI wafer supplier in their fabrication methods. They show how researchers used the device layer, BOX and handle to build different membrane structures.

Thin silicon membranes for thermal-transport experiments

Ravichandran, Zhang and Minnich used SOI wafers from MEMS Engineering and Materials Inc. to fabricate suspended silicon membranes for a study of thermal phonon reflections. Their process removed handle silicon beneath a window, then removed the BOX to release the device silicon. The paper reports three finished membrane thicknesses: 515, 590 and 1,145 nm.

This is a concrete example of the BOX serving as an intermediate etch stop before membrane release. Those thicknesses describe the researchers’ fabricated samples, not a uniformity specification for our current stock.

Ravichandran, Zhang & Minnich, Spectrally Resolved Specular Reflections of Thermal Phonons from Atomically Rough Surfaces. Physical Review X 8, 041004 (2018), Section III.

A defined SOI stack for a microfluidic oxygenator prototype

Blauvelt and colleagues report purchasing SOI wafers from MEMS Engineering & Material, Inc. in Sunnyvale for silicon membrane fabrication. Their starting stack had a 100 µm device layer, 1 µm BOX and 299 µm handle. The researchers patterned and etched pores into the device silicon and larger windows into the handle, using the buried oxide as an etch boundary.

The stack illustrates why an SOI inquiry should specify all three layers separately: the thin oxide and the two silicon layers had distinct roles in the fabrication flow. The paper describes a research prototype and its testing, rather than a commercially approved medical device.

Blauvelt et al., A silicon membrane microfluidic oxygenator for use as an artificial placenta with minimal anticoagulation. Bioengineering & Translational Medicine 10, e70037 (2025), Section 5.1.

These references document published use of our wafers; they do not imply endorsement by the authors or their institutions. For your own design, compare current SOI lot specifications or use our layer-by-layer specification checklist.

How the layers are brought together

Bonding and thinning

Bonded SOI can be formed by joining silicon wafers with an oxide layer at the interface, then thinning one silicon wafer to make the device layer. Bonding and the subsequent thickness-control steps determine the resulting stack. MEMS Engineering offers bonded SOI with stock and custom specifications.

Layer transfer

Smart Cut™ is Soitec’s layer-transfer technology. It combines light-ion implantation with wafer bonding to transfer a thin single-crystal layer to another substrate. The donor can be prepared for reuse. Soitec explains the process here. This describes a manufacturing approach, not the process used for every SOI product.

Process names alone do not define an interchangeable wafer. Compare the finished layer specifications and required inspection data, then confirm process-specific constraints with the supplier.

Should you choose SOI or bulk silicon?

Choose around the fabrication flow. A buried oxide is useful when your design needs that interface; it also introduces another material and another thickness to account for. If your process does not use a buried insulating layer, a bulk substrate may meet the requirement with a simpler wafer specification.

For example, if a MEMS design calls for a 10 µm silicon structure above a removable oxide, compare the SOI device-layer thickness and tolerance with that design requirement. A 10 µm nominal layer alone does not establish that a lot fits: the BOX, handle, electrical properties and release process still need to match. This is an illustrative selection example, not a product recommendation.

For either substrate, processing both faces also requires checking the backside finish and handling requirements. Compare SOI stock specifications with the silicon wafer range before deciding which structure fits your process.

There is no universal SOI price or lead time. A stock lot and a custom stack are different purchasing decisions. At MEMS Engineering, SOI pricing and availability are confirmed by quotation.

Turn the design into a wafer specification

A useful inquiry names the diameter and the device, BOX and handle requirements independently. Add doping, resistivity, orientation, finish and the tolerances your process actually needs. Mark unresolved requirements as questions rather than silently accepting a catalog default.

Continue with our SOI specification checklist for a worked inventory example. If your requirements are already defined, compare available SOI lots or request a custom SOI quote.